US 11,810,945 B2
Trench capacitor and method of forming the same
Tao-Cheng Liu, Hsinchu (TW); Shih-Chi Kuo, Hsinchu (TW); Tsai-Hao Hung, Hsinchu (TW); and Tsung-Hsien Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Dec. 9, 2020, as Appl. No. 17/116,823.
Application 17/116,823 is a continuation of application No. 15/627,614, filed on Jun. 20, 2017, granted, now 10,868,107.
Prior Publication US 2021/0118978 A1, Apr. 22, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 29/94 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01)
CPC H01L 28/40 (2013.01) [H01L 21/76879 (2013.01); H01L 27/0805 (2013.01); H01L 28/90 (2013.01); H01L 29/945 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, the method comprising:
etching a substrate to define a first trench and a second trench;
depositing a first number M of capacitor layer pairs in the first trench, wherein each of the first number M of capacitor layer pairs comprises:
a first dielectric layer, and
a first conductive layer;
depositing a second number N of capacitor layer pairs in the second trench, wherein the second number N is different from the first number M, and each of the second number N of capacitor layer pairs comprises:
a second dielectric layer, and
a second conductive layer; and
planarizing the first number M of capacitor layer pairs and the second number N of capacitor layer pairs to expose the substrate.