US 11,810,917 B2
Self-aligned etch in semiconductor devices
Yi-Hsun Chiu, Zhubei (TW); Ching-Wei Tsai, Hsinchu (TW); Yu-Xuan Huang, Hsinchu (TW); Cheng-Chi Chuang, New Taipei (TW); and Shang-Wen Chang, Jhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 29, 2022, as Appl. No. 17/733,169.
Application 17/733,169 is a continuation of application No. 16/944,025, filed on Jul. 30, 2020, granted, now 11,342,326.
Claims priority of provisional application 63/016,391, filed on Apr. 28, 2020.
Prior Publication US 2022/0262794 A1, Aug. 18, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 21/768 (2006.01); H01L 23/535 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/7682 (2013.01); H01L 23/535 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a first transistor structure, the first transistor structure comprising a semiconductor fin, a gate structure on the semiconductor fin, and a source/drain region in the semiconductor fin adjacent the gate structure;
forming a backside interconnect structure on a backside of the first transistor structure, wherein forming the backside interconnect structure comprises:
removing an isolation structure surrounding the semiconductor fin and the source/drain region;
forming first spacers along sidewalls of the semiconductor fin and the source/drain region;
etching the source/drain region using the first spacers as a mask; and
forming a dielectric layer surrounding the semiconductor fin, the source/drain region, and the first spacers.