US 11,810,908 B2
Wafer-level 3D integration of high voltage optical transformer
Christopher Yuan Ting Liao, Seattle, WA (US); Maik Andre Scheller, Redmond, WA (US); Jonathan Robert Peterson, Woodinville, WA (US); Ehsan Vadiee, Redmond, WA (US); John Goward, Redmond, WA (US); Anurag Tyagi, Kirkland, WA (US); and Andrew John Ouderkirk, Kirkland, WA (US)
Assigned to Meta Platforms Technologies, LLC, Menlo Park, CA (US)
Filed by META PLATFORMS TECHNOLOGIES, LLC, Menlo Park, CA (US)
Filed on May 21, 2021, as Appl. No. 17/326,777.
Prior Publication US 2022/0375910 A1, Nov. 24, 2022
Int. Cl. H01L 25/16 (2023.01); H01L 31/02 (2006.01); H01L 31/0224 (2006.01); H01L 31/04 (2014.01); H01L 31/18 (2006.01)
CPC H01L 25/167 (2013.01) [H01L 31/02021 (2013.01); H01L 31/022425 (2013.01); H01L 31/04 (2013.01); H01L 31/18 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method comprising:
forming a via through a transparent carrier wafer;
forming a conductive layer within the via;
bonding a solid state lighting (SSL) package to a first side of the carrier wafer;
bonding a photovoltaic (PV) wafer to a second side of the carrier wafer opposite to the first side, wherein the photovoltaic wafer comprises an active area and a conductive area located outside of the active area, the conductive area being in electrical contact with the conductive layer;
forming an SSL contact over the solid state lighting package on the first side of the carrier wafer; and
forming a PV contact over the conductive layer on the first side of the carrier wafer.