US 11,810,884 B2
High density substrate routing in package
Weng Hong Teh, Cambridge, MA (US); and Chia-Pin Chiu, Tempe, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 6, 2022, as Appl. No. 17/570,255.
Application 14/663,689 is a division of application No. 13/707,159, filed on Dec. 6, 2012, granted, now 9,190,380, issued on Nov. 17, 2015.
Application 17/570,255 is a continuation of application No. 17/077,996, filed on Oct. 22, 2020, granted, now 11,251,150.
Application 17/077,996 is a continuation of application No. 16/561,965, filed on Sep. 5, 2019, granted, now 10,861,815, issued on Dec. 8, 2020.
Application 16/561,965 is a continuation of application No. 16/239,670, filed on Jan. 4, 2019, granted, now 10,438,915, issued on Oct. 8, 2019.
Application 16/239,670 is a continuation of application No. 15/873,567, filed on Jan. 17, 2018, granted, now 10,199,346, issued on Feb. 5, 2019.
Application 15/873,567 is a continuation of application No. 15/255,351, filed on Sep. 2, 2016, granted, now 9,929,119, issued on Mar. 27, 2018.
Application 15/255,351 is a continuation of application No. 14/922,425, filed on Oct. 26, 2015, granted, now 9,437,569, issued on Sep. 6, 2016.
Application 14/922,425 is a continuation of application No. 14/663,689, filed on Mar. 20, 2015, granted, now 9,171,816, issued on Oct. 27, 2015.
Prior Publication US 2022/0130789 A1, Apr. 28, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 25/16 (2023.01); H01L 23/50 (2006.01); H01L 25/18 (2023.01); H01L 21/56 (2006.01)
CPC H01L 24/25 (2013.01) [H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/50 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/2501 (2013.01); H01L 2224/2505 (2013.01); H01L 2224/255 (2013.01); H01L 2224/2512 (2013.01); H01L 2224/73209 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/92133 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/141 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15151 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15747 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/18162 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first dielectric layer including through vias therein, the through vias having a first pitch;
a high density interconnect structure in the first dielectric layer, the high density interconnect structure between a first portion and a second portion of the through vias in the first dielectric layer, the high density interconnect structure having interconnect pads having a second pitch less than the first pitch;
a second dielectric layer on the first dielectric layer, the second dielectric layer having a top surface;
a first die in the second dielectric layer, the first die coupled to the first portion of the through vias in the first dielectric layer and coupled to a first portion of the interconnect pads of the high density interconnect structure, and the first die having a top surface co-planar with the top surface of the second dielectric layer; and
a second die in the second dielectric layer, the second die coupled to the second portion of the through vias in the first dielectric layer and coupled to a second portion of the interconnect pads of the high density interconnect structure, wherein the interconnect pads of the high density interconnect structure face towards the first die and the second die.