US 11,810,877 B2
Integrated decoupling capacitors
Vipulkumar K. Patel, Breinigsville, PA (US); Mark A. Webster, Bethlehem, PA (US); and Craig S. Appel, Macungie, PA (US)
Assigned to Cisco Technology, Inc., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Nov. 15, 2021, as Appl. No. 17/454,937.
Application 17/454,937 is a division of application No. 16/809,446, filed on Mar. 4, 2020, granted, now 11,227,847.
Prior Publication US 2022/0077084 A1, Mar. 10, 2022
Int. Cl. H01L 23/64 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 21/20 (2006.01); G02B 6/122 (2006.01); G02B 6/12 (2006.01); G02B 6/30 (2006.01)
CPC H01L 24/01 (2013.01) [H01L 21/2007 (2013.01); H01L 23/5222 (2013.01); G02B 6/1225 (2013.01); G02B 6/305 (2013.01); G02B 2006/12061 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A combination wafer, comprising:
a first wafer comprising an optical modulator; and
a second wafer comprising a decoupling capacitor, wherein the first wafer and the second wafer are directly bonded along a wafer bond line,
wherein the first wafer comprises a plurality of vias that electrically connect the decoupling capacitor in the second wafer to bond pads disposed on a first side of the first wafer that is opposite the wafer bond line,
wherein the second wafer is a semiconductor wafer and the first wafer comprises a photonic chip that includes the optical modulator.