US 11,810,876 B1
Heterogeneous integration of radio frequency transistor chiplets having interconnection tuning circuits
James Buckwalter, Santa Barbara, CA (US); Michael Hodge, Huntersville, NC (US); Justin Kim, San Jose, CA (US); Florian Herrault, Agoura Hills, CA (US); and Daniel Green, McLean, VA (US)
Assigned to PseudolithIC, Inc., Santa Barbara, CA (US)
Filed by PseudolithIC, Inc., Santa Barbara, CA (US)
Filed on Mar. 10, 2023, as Appl. No. 18/182,314.
Int. Cl. H01L 23/66 (2006.01); H03H 7/38 (2006.01)
CPC H01L 23/66 (2013.01) [H03H 7/38 (2013.01); H01L 2223/6605 (2013.01); H01L 2223/6661 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic assembly for heterogeneous integration of radio frequencies (RF) transistor chiplets having interconnections to or between tuning circuits, the assembly comprising:
a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks;
at least one chiplet having a second circuit including at least two RF transistors or two RF switch devices and passive tuning circuits for each of the at least two RF transistors or two RF switch devices, each passive tuning circuit including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network; and
electrical interconnects between the chiplets and the wafer, wherein the electrical interconnects electrically connect the first circuit to the second circuit.