US 11,810,869 B2
Semiconductor device and method of manufacturing the same
Kazuo Tomita, Tokyo (JP); and Hiroki Takewaka, Tokyo (JP)
Assigned to RENESAS ELECTRONICS CORPORATION, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Sep. 21, 2022, as Appl. No. 17/949,460.
Application 17/949,460 is a continuation of application No. 16/950,560, filed on Nov. 17, 2019, granted, now 11,482,498.
Application 16/950,560 is a continuation of application No. 16/365,354, filed on Mar. 26, 2019, granted, now 10,923,437, issued on Feb. 16, 2021.
Application 16/365,354 is a continuation of application No. 15/676,945, filed on Aug. 14, 2017, granted, now 10,283,458, issued on May 7, 2019.
Application 15/676,945 is a continuation of application No. 15/177,318, filed on Jun. 8, 2016, granted, now 9,761,541, issued on Sep. 12, 2017.
Application 15/177,318 is a continuation of application No. 14/685,886, filed on Apr. 14, 2015, granted, now 9,391,035, issued on Jul. 12, 2016.
Claims priority of application No. 2014-082804 (JP), filed on Apr. 14, 2014.
Prior Publication US 2023/0015101 A1, Jan. 19, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 21/66 (2006.01); H01L 23/495 (2006.01); H01L 23/544 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4825 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 22/12 (2013.01); H01L 23/3114 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49562 (2013.01); H01L 23/544 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/09 (2013.01); H01L 24/46 (2013.01); H01L 22/32 (2013.01); H01L 23/3192 (2013.01); H01L 24/02 (2013.01); H01L 24/45 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/02166 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/06133 (2013.01); H01L 2224/06155 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/4905 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01)] 40 Claims
OG exemplary drawing
 
1. A semiconductor chip comprising:
a first pad;
a first lead-out wiring portion integrally formed with the first pad, the first lead-out wiring portion connected to a lower-layer wiring through a first contact;
a sloped portion formed on a connection part between the first pad and the first lead-out wiring portion;
a surface protective film covering the first lead-out wiring portion, the surface protective film on which a first opening is formed to expose a part of a surface of the first pad; and
a second pad formed next to the first pad along an edge side of the semiconductor chip,
wherein a central position of a width of the first lead-out wiring portion is shifted relative to a central position of a side to which the first lead-out wiring portion is connected among a plurality of sides making up the first pad, and
wherein a connection angle of the connection part between the first pad and the first lead-out wiring portion is comprised of obtuse angles formed at two spots,
wherein a second opening is formed on the surface protective film to expose a part of a surface of the second pad, and
wherein, in plan view, a difference between a size of the first pad and a size of the second pad is larger than a difference between a size of the first opening and a size of the second opening.