US 11,810,827 B2
FinFET device with different liners for PFET and NFET and method of fabricating thereof
Ming-Lung Cheng, Kaohsiung County (TW); Yen-Chun Lin, Hsinchu (TW); and Da-Wen Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 4, 2021, as Appl. No. 17/338,929.
Application 16/045,992 is a division of application No. 15/725,544, filed on Oct. 5, 2017, granted, now 10,522,417, issued on Dec. 31, 2019.
Application 17/338,929 is a continuation of application No. 16/045,992, filed on Jul. 26, 2018, granted, now 11,031,299.
Claims priority of provisional application 62/490,839, filed on Apr. 27, 2017.
Prior Publication US 2021/0366784 A1, Nov. 25, 2021
Int. Cl. H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01)
CPC H01L 21/823821 (2013.01) [H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/1054 (2013.01); H01L 29/7843 (2013.01); H01L 29/7846 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/31105 (2013.01); H01L 21/31144 (2013.01); H01L 21/823892 (2013.01); H01L 27/0928 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor formed over a first well, wherein the first transistor includes a first fin structure;
a second transistor formed over a second well, wherein the first well and the second well are doped oppositely, the second transistor includes a second fin structure that contains silicon and doped silicon;
an isolation structure formed over the first well, over the second well, and between the first transistor and the second transistor;
a first number of liner layers disposed between the first transistor and the isolation structure; and
a second number of liner layers disposed between the second transistor and the isolation structure, wherein the second number is less than the first number, and wherein an innermost side surface of the second number of liner layers is in direct contact with a portion, but not all, of a silicon side surface of the second fin structure, and wherein the innermost side surface of the second number of liner layers is in direct contact with an entirety of a doped silicon side surface of the second fin structure.