US 11,810,825 B2
Methods of forming epitaxial structures in fin-like field effect transistors
Feng-Ching Chu, Pingtung County (TW); Wei-Yang Lee, Taipei (TW); Feng-Cheng Yang, Hsinchu County (TW); and Yen-Ming Chen, Hsin-Chu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 25, 2021, as Appl. No. 17/411,937.
Application 16/696,121 is a division of application No. 15/939,647, filed on Mar. 29, 2018, granted, now 10,497,628, issued on Dec. 3, 2019.
Application 17/411,937 is a continuation of application No. 16/696,121, filed on Nov. 26, 2019, granted, now 11,107,735.
Claims priority of provisional application 62/589,664, filed on Nov. 22, 2017.
Prior Publication US 2021/0384081 A1, Dec. 9, 2021
Int. Cl. H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/823814 (2013.01) [H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first fin structure protruding from a semiconductor substrate;
a second fin structure protruding from the semiconductor substrate and adjacent to the first fin structure;
a p-type source/drain feature over the first fin structure;
an n-type source/drain feature over the second fin structure;
isolation features separating bottom portions of the p-type source/drain feature and the n-type source/drain feature; and
an interlayer dielectric (ILD) layer disposed over the p-type and the n-type source/drain features, wherein a portion of the ILD layer is disposed below a portion of the isolation features that is between the p-type and the n-type source/drain features.