US 11,810,818 B2
Metal interconnect structure and method for fabricating the same
Da-Jun Lin, Kaohsiung (TW); and Bin-Siang Tsai, Changhua County (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Mar. 9, 2021, as Appl. No. 17/195,648.
Application 17/195,648 is a division of application No. 16/011,615, filed on Jun. 18, 2018, granted, now 10,978,339.
Claims priority of application No. 107117189 (TW), filed on May 21, 2018.
Prior Publication US 2021/0202307 A1, Jul. 1, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76858 (2013.01) [H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76846 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/53238 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method for fabricating semiconductor device, comprising:
forming a dielectric layer on a substrate;
forming a trench in the dielectric layer;
forming a second liner in the trench;
forming a third liner on the second liner;
performing an anneal process to transform the second liner and the third liner into a first liner in the trench, wherein the first liner comprises Co—Ru alloy;
forming a metal layer on the first liner, wherein the Co—Ru alloy contacts the metal layer directly; and
planarizing the metal layer and the first liner to form a metal interconnection.