US 11,810,816 B2
Chemical mechanical polishing topography reset and control on interconnect metal lines
Shih-Kang Fu, Hsinchu (TW); and Ming-Han Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on May 13, 2022, as Appl. No. 17/744,545.
Application 17/744,545 is a continuation of application No. 17/033,270, filed on Sep. 25, 2020, granted, now 11,342,219.
Prior Publication US 2022/0270915 A1, Aug. 25, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
forming a via in a first portion of a first dielectric layer over a substrate, wherein the first dielectric layer has a non-planar surface such that a surface of the first portion of the first dielectric layer is below a surface of a second portion of the first dielectric layer adjacent to the first portion;
conformally depositing a conductive material layer over the first dielectric layer and the via, the conductive material layer having a non-planar surface conforming to the non-planar surface of the first dielectric layer;
planarizing the conductive material layer to provide a planar surface across the substrate;
etching the conductive material layer to form a first conductive line overlying the first portion of the first dielectric layer in contact with the via and a second conductive line overlying the second portion of the first dielectric layer; and
forming a second dielectric layer surrounding the first conducive line and the second conductive line.