CPC H01L 21/7682 (2013.01) [H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/5329 (2013.01); H01L 23/53209 (2013.01); H01L 23/53223 (2013.01); H01L 23/53238 (2013.01); H01L 23/53252 (2013.01); H01L 23/53266 (2013.01)] | 20 Claims |
1. A method for forming a semiconductor structure, comprising:
forming a via in a first portion of a first dielectric layer over a substrate, wherein the first dielectric layer has a non-planar surface such that a surface of the first portion of the first dielectric layer is below a surface of a second portion of the first dielectric layer adjacent to the first portion;
conformally depositing a conductive material layer over the first dielectric layer and the via, the conductive material layer having a non-planar surface conforming to the non-planar surface of the first dielectric layer;
planarizing the conductive material layer to provide a planar surface across the substrate;
etching the conductive material layer to form a first conductive line overlying the first portion of the first dielectric layer in contact with the via and a second conductive line overlying the second portion of the first dielectric layer; and
forming a second dielectric layer surrounding the first conducive line and the second conductive line.
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