US 11,810,793 B2
Semiconductor packages and methods of forming same
Chung-Yu Lu, Hsinchu (TW); Ping-Kang Huang, Chiayi (TW); Sao-Ling Chiu, Hsinchu (TW); and Shang-Yun Hou, Jubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/873,640.
Application 17/873,640 is a continuation of application No. 17/065,265, filed on Oct. 7, 2020, granted, now 11,495,472.
Claims priority of provisional application 63/010,846, filed on Apr. 16, 2020.
Prior Publication US 2022/0367208 A1, Nov. 17, 2022
Int. Cl. H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H01L 25/18 (2023.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01)
CPC H01L 21/486 (2013.01) [H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 23/49827 (2013.01); H01L 23/5384 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 21/563 (2013.01); H01L 23/49894 (2013.01); H01L 2224/81815 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a first through via in a substrate, the first through via extending into a first side of the substrate;
attaching a first die to the first side of the substrate;
recessing a second side of the substrate to expose the first through via; and
forming a polymer layer on the second side of the substrate;
forming a metallization pattern in the polymer layer;
forming a first set of conductive bumps on the polymer layer, at least one of the first set of conductive bumps being electrically coupled to the metallization pattern and the exposed first through via;
after the recessing the second side of the substrate, forming a first dielectric layer on sidewalls of the first through via and on the recessed second side of the substrate; and
forming a second dielectric layer on the first dielectric layer, the polymer layer being on the second dielectric layer.