US 11,810,784 B2
Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer
Marek Hytha, Brookline, MA (US); Keith Doran Weeks, Chandler, AZ (US); Nyles Wynn Cody, Tempe, AZ (US); and Hideki Takeuchi, San Jose, CA (US)
Assigned to ATOMERA INCORPORATED, Los Gatos, CA (US)
Filed by Atomera Incorporated, Los Gatos, CA (US)
Filed on Apr. 21, 2021, as Appl. No. 17/236,289.
Prior Publication US 2022/0344155 A1, Oct. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/02 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 21/02507 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H01L 21/8234 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A method for making a semiconductor device comprising:
forming a first single crystal silicon layer having a first percentage of silicon 28;
forming a superlattice above the first single crystal silicon layer, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions; and
forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.