US 11,810,641 B2
Apparatuses and method for trimming input buffers based on identified mismatches
Christian N. Mohr, Allen, TX (US); Jennifer E. Taylor, Boise, ID (US); and Vijayakrishna J. Vankayala, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 10, 2020, as Appl. No. 16/926,505.
Application 16/926,505 is a continuation of application No. 16/121,325, filed on Sep. 4, 2018, granted, now 10,714,156.
Prior Publication US 2020/0342922 A1, Oct. 29, 2020
Int. Cl. G11C 7/10 (2006.01); G11C 11/4093 (2006.01); H03F 3/45 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/1096 (2013.01); G11C 11/4093 (2013.01); H03F 3/45475 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a buffer having an input stage circuit configured to receive a first signal and to provide an output based on the first signal, wherein the buffer further comprises an output stage coupled to the input stage circuit and is configured to provide an output signal based on the output of the input stage, wherein the input stage circuit comprises a plurality of serially-coupled transistor pairs that are each selectively enabled in response to a respective enable signal, and wherein the serially-coupled transistor pairs are coupled to one another in parallel; and
a trim circuit configured to provide the respective enable signals to adjust a transition voltage of the input stage circuit based on a detected transition voltage offset relative to a target transition voltage.