US 11,810,635 B2
Sense amplifier for coupling effect reduction
Ku-Feng Lin, Hsinchu (TW); Jui-Che Tsai, Hsinchu County (TW); Perng-Fei Yuh, Walnut Creek, CA (US); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 2, 2023, as Appl. No. 18/163,461.
Application 18/163,461 is a continuation of application No. 17/407,451, filed on Aug. 20, 2021, granted, now 11,601,117.
Prior Publication US 2023/0179186 A1, Jun. 8, 2023
Int. Cl. G11C 7/06 (2006.01); H03K 3/356 (2006.01); H01L 27/06 (2006.01); H03K 3/037 (2006.01)
CPC G11C 7/065 (2013.01) [H01L 27/0629 (2013.01); H03K 3/037 (2013.01); H03K 3/35613 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a first input transistor having a first input gate and a first drain/source terminal;
a second input transistor having a second input gate and a second drain/source terminal;
a latch circuit including:
a first latch transistor having a third drain/source terminal connected to the first drain/source terminal; and
a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal; and
at least two capacitors connected in parallel, the at least two capacitors including:
a first transistor capacitor having a drain and a source connected at a first terminal and a gate at a second terminal, wherein the first terminal is connected to one of the first input gate and the fourth drain/source terminal and the second terminal is connected to the other one of the first input gate and the fourth drain/source terminal; and
a first polycrystalline silicon gate to polycrystalline silicon gate capacitor including:
a first polycrystalline silicon gate connected to a first metal layer line; and
a second polycrystalline silicon gate connected to a second metal layer line, wherein the first metal layer line is connected to one of the first input gate and the fourth drain/source terminal and the second metal layer line is connected to the other one of the first input gate and the fourth drain/source terminal.