CPC G11C 7/065 (2013.01) [H01L 27/0629 (2013.01); H03K 3/037 (2013.01); H03K 3/35613 (2013.01)] | 20 Claims |
1. A device, comprising:
a first input transistor having a first input gate and a first drain/source terminal;
a second input transistor having a second input gate and a second drain/source terminal;
a latch circuit including:
a first latch transistor having a third drain/source terminal connected to the first drain/source terminal; and
a second latch transistor having a fourth drain/source terminal connected to the second drain/source terminal; and
at least two capacitors connected in parallel, the at least two capacitors including:
a first transistor capacitor having a drain and a source connected at a first terminal and a gate at a second terminal, wherein the first terminal is connected to one of the first input gate and the fourth drain/source terminal and the second terminal is connected to the other one of the first input gate and the fourth drain/source terminal; and
a first polycrystalline silicon gate to polycrystalline silicon gate capacitor including:
a first polycrystalline silicon gate connected to a first metal layer line; and
a second polycrystalline silicon gate connected to a second metal layer line, wherein the first metal layer line is connected to one of the first input gate and the fourth drain/source terminal and the second metal layer line is connected to the other one of the first input gate and the fourth drain/source terminal.
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