US 11,810,630 B2
Machine learning assisted read verify in a memory sub-system
Amit Bhardwaj, Hyderabad (IN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 10, 2021, as Appl. No. 17/523,523.
Claims priority of application No. 202141039710 (IN), filed on Sep. 2, 2021.
Prior Publication US 2023/0061920 A1, Mar. 2, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G06N 20/00 (2019.01); G11C 29/18 (2006.01); G11C 16/26 (2006.01); G06F 18/21 (2023.01); G06F 18/243 (2023.01)
CPC G11C 16/3495 (2013.01) [G06F 18/2178 (2023.01); G06F 18/24323 (2023.01); G06N 20/00 (2019.01); G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 29/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a plurality of planes; and
a processing device, operatively coupled with the of memory device, to perform operations comprising:
detecting an on-chip copy command, wherein the on-chip copy command comprises a source address referencing a plane of the plurality of planes and a destination address referencing the plane;
estimating a read verify relevance by processing, by a machine learning model, one or more parameters associated with data stored at the source address; and
responsive to determining that the read verify relevance satisfies a threshold condition, performing the on-chip copy command.