| CPC G11C 16/3445 (2013.01) [G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] | 20 Claims |
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1. A non-volatile storage apparatus, comprising:
a plurality of word lines;
a block of non-volatile memory cells comprising multiple sub-blocks, each sub-block includes NAND strings connected to the plurality of word lines; and
a control circuit connected to the block of non-volatile memory cells and the plurality of word lines, the control circuit is configured to:
concurrently erase the NAND strings of the multiple sub-blocks,
perform an erase verify process for the NAND strings of the multiple sub-blocks including separately performing erase verify for memory cells connected to even word lines to generate an even result for each NAND string and performing erase verify for memory cells connected to odd word lines to generate an odd result for each NAND string,
determine that the erasing of the memory cells for a first sub-block of the multiple sub-blocks erase verified successfully when a sum of NAND strings of the first sub-block that failed the erase verify process for memory cells connected to even word lines or failed the erase verify process for memory cells connected to odd word lines is below a first threshold,
determine that the erasing of the first sub-block failed, despite determining that the memory cells for the first sub-block erase verified successfully, if a number of NAND strings of the first sub-block that have the even result different than the odd result is greater than a second threshold, and
determine that the erasing of one or more additional sub-blocks of the multiple sub-blocks failed based on and in response to determining that the erasing of the first sub-block failed.
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