US 11,810,618 B2
Extended memory communication
Vijay S. Ramesh, Boise, ID (US); and Allan Porterfield, Durham, NC (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 1, 2021, as Appl. No. 17/453,136.
Application 17/453,136 is a continuation of application No. 17/109,999, filed on Dec. 2, 2020, granted, now 11,164,625.
Application 17/109,999 is a continuation of application No. 16/744,541, filed on Jan. 16, 2020, granted, now 10,910,048, issued on Feb. 2, 2021.
Prior Publication US 2022/0059163 A1, Feb. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01); G06F 9/54 (2006.01); G06F 9/30 (2018.01); G06F 7/57 (2006.01)
CPC G11C 13/0023 (2013.01) [G06F 7/57 (2013.01); G06F 9/3001 (2013.01); G06F 9/542 (2013.01); G06F 9/546 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/71 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving, at a processing unit that is coupled between a host device and a memory device, first signaling indicative of performance of an operation using data written to or read from the memory device;
performing, at the processing unit, the operation in response to the signaling; and
transmitting, to a logic device external to the processing unit, second signaling indicative of performance of one or more additional operations using the data written to or read from the memory device, wherein the transmitted additional signaling includes a first portion of a command to perform the one or more additional operations by the logic device.