US 11,809,872 B2
Thread commencement using a work descriptor packet in a self-scheduling processor
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 25, 2021, as Appl. No. 17/384,767.
Application 17/384,767 is a continuation of application No. 16/399,615, filed on Apr. 30, 2019, granted, now 11,119,782.
Claims priority of provisional application 62/667,679, filed on May 7, 2018.
Prior Publication US 2021/0357230 A1, Nov. 18, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 15/82 (2006.01); G06F 9/30 (2018.01); G06F 12/0875 (2016.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 13/40 (2006.01)
CPC G06F 9/3836 (2013.01) [G06F 9/30101 (2013.01); G06F 9/4881 (2013.01); G06F 9/542 (2013.01); G06F 9/546 (2013.01); G06F 12/0875 (2013.01); G06F 13/4027 (2013.01); G06F 15/82 (2013.01); G06F 2212/452 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor core configured to execute a plurality of instructions; and
a core control circuit coupled to the processor core, the core control circuit comprising:
an interconnection network interface coupleable to an interconnection network to receive a work descriptor data packet, the interconnection network interface configured to decode the received work descriptor data packet into a received program count and at least one received argument for a corresponding execution thread
a first, thread control memory circuit comprising a thread identifier pool register configured to store a plurality of thread identifiers, a program count register configured to store the received program count for the corresponding execution thread, and a data cache or a general-purpose register configured to store the at least one received argument for the corresponding execution thread;
an execution queue coupled to the thread control memory circuit, the execution queue configured to store one or more thread identifiers, of the plurality of thread identifiers; and
a control logic and thread selection circuit coupled to the execution queue, the control logic and thread selection circuit configured, in response to receiving the work descriptor data packet having the received program count and the at least one received argument, to automatically schedule execution of the corresponding execution thread by assigning a thread identifier of the plurality of thread identifiers to the corresponding execution thread, placing the thread identifier in the execution queue, and to periodically selecting the thread identifier of the one or more thread identifiers in the execution queue for execution by the processor core of an instruction of the corresponding execution thread, of the plurality of instructions, the processor core commencing automatic execution of the instruction corresponding to the received program count using the at least one received argument of the corresponding execution thread.