CPC G06F 9/30145 (2013.01) [G06F 9/30036 (2013.01); G06F 9/30043 (2013.01)] | 22 Claims |
1. A processor comprising:
decode circuitry configured to decode a single store matrix pair instruction specifying an opcode, a first source matrix identifier, and a destination identifier; and
the execution circuitry configured to execute the decoded store matrix pair instruction as per the opcode to:
determine that a pair of matrices are to be stored to memory based on a value, the pair of matrices including a first two-dimensional source matrix and a second two-dimensional source matrix; and
store elements from element positions of the first two-dimensional source matrix to corresponding element positions of a first two-dimensional destination matrix in the memory, and store elements from element positions of the second two-dimensional source matrix to corresponding element positions of a second two-dimensional destination matrix in the memory, in response to the determination that the pair of matrices are to be stored to the memory based on the value.
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