CPC G06F 30/398 (2020.01) [G06F 30/394 (2020.01); G06F 30/367 (2020.01)] | 20 Claims |
1. A failure-in-time (FIT) evaluation method for an integrated circuit (IC), comprising:
accessing data representing a layout of the IC that comprises a metal line and a plurality of vertical interconnect accesses (VIAs), wherein the metal line is a straight line in a metal layer and is divided into a first sub-line with a first line width and a second sub-line with a second line width;
picking a plurality of nodes along the first and second sub-lines of the metal line;
dividing the metal line into a plurality of metal segments based on the nodes; and
determining FIT value for each of the metal segments to verify the layout and fabricate the IC,
wherein the first line width of the first sub-line is greater than the second line width of the second sub-line in a first direction,
wherein one of the metal segments comprises a portion of the first sub-line with the first line width and a portion of the second sub-line with the second line width, and the one of the metal segments is longer than the metal segment comprising the remaining first sub-line and the metal segment comprising the remaining second sub-line in a second direction, and the second direction is perpendicular to the first direction.
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