US 11,809,800 B2
Interface for data communication between chiplets or other integrated circuits on an interposer
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 1, 2022, as Appl. No. 17/958,343.
Application 17/958,343 is a continuation of application No. 16/266,033, filed on Feb. 2, 2019, granted, now 11,461,527.
Claims priority of provisional application 62/625,520, filed on Feb. 2, 2018.
Prior Publication US 2023/0042222 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 30/394 (2020.01); G11C 7/10 (2006.01); G11C 11/409 (2006.01); H04L 69/18 (2022.01); H04L 69/12 (2022.01); H04L 9/40 (2022.01)
CPC G06F 30/394 (2020.01) [G11C 7/1045 (2013.01); G11C 11/409 (2013.01); H04L 9/40 (2022.05); H04L 69/12 (2013.01); H04L 69/18 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A method of data communication on a communication link coupling a first integrated circuit to a second integrated circuit arranged on an interposer, the method comprising:
using a parallel flit interface, receiving a first parallel data and control packet from a communication network;
using a multiplexer coupled to the parallel flit interface, converting the first parallel data and control packet to a first serial data and control packet comprising a first plurality of serial flits;
using a transmitter coupled to a communication link, sequentially transmitting the first plurality of serial flits over the communication link;
using a receiver coupled to the communication link, receiving a second plurality of serial flits of a second serial data and control packet; and
using a demultiplexer coupled to the parallel flit interface and to the receiver, converting the second plurality of serial flits to a second parallel data and control packet for transmission on the communication network;
wherein the first and second parallel data and control packets each comprise at least one flit having an ordered plurality of fields.