| CPC G06F 3/0659 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0652 (2013.01); G06F 3/0673 (2013.01)] | 14 Claims |
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1. A memory controller, comprising:
a command queue having a first input for receiving memory access requests;
a memory interface queue having an output for coupling to a memory channel adapted for coupling to a dynamic random access memory (DRAM);
an arbiter coupled to the command queue for selecting entries from the command queue, and placing them in the memory interface queue causing them to be transmitted over the memory channel; and
a refresh control circuit coupled to the arbiter and operable to:
monitor activate commands to be sent over the memory channel;
in response to an activate command meeting a designated condition, identify a candidate aggressor row associated with the activate command; and
transmit a command to the DRAM identifying the candidate aggressor row and requesting that the candidate aggressor row be queued for mitigation in a future refresh or refresh management event, wherein transmitting the command to the DRAM includes tagging an activate command that includes a row address of the candidate aggressor row.
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