US 11,809,719 B2
Techniques for performing write training on a dynamic random-access memory
Gautam Bhatia, Mountain View, CA (US); and Robert Bloemer, Sterling, MA (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Dec. 14, 2021, as Appl. No. 17/550,811.
Application 17/550,811 is a continuation in part of application No. 17/523,779, filed on Nov. 10, 2021.
Claims priority of provisional application 63/179,954, filed on Apr. 26, 2021.
Claims priority of provisional application 63/152,817, filed on Feb. 23, 2021.
Claims priority of provisional application 63/152,814, filed on Feb. 23, 2021.
Claims priority of provisional application 63/144,971, filed on Feb. 2, 2021.
Prior Publication US 2022/0244863 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for performing a write training operation on a memory device, the method comprising:
initializing a read/write memory on the memory device with a first data pattern based on a seed value stored in a first register;
receiving a second data pattern on an input pin of the memory device;
comparing the first data pattern with the second data pattern to generate a results value; and
storing the results value in a second register, wherein the results value specifies whether the write training operation was successful.