CPC G06F 3/0613 (2013.01) [G06F 3/0631 (2013.01); G06F 3/0652 (2013.01); G06F 3/0683 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01)] | 20 Claims |
1. A system comprising:
a plurality of memory devices; and
a processing device coupled to the plurality of memory devices, the processing device to perform operations comprising:
receiving an input/output (I/O) write request directed at the plurality of memory devices, wherein the I/O write request comprises a first data object, wherein the plurality of memory devices comprises a plurality of groups of memory cells corresponding to sequential logical addresses, and wherein each group of memory cells of the plurality of groups of memory cells is associated with an available capacity state indicating at least one of: a full state or a not-full state;
appending the first data object to a compound data object, wherein the compound data object comprises one or more sequentially written data objects;
identifying, based on an order corresponding to the sequential logical addresses, a first group of memory cells of the plurality of groups of memory cells, wherein the first group of memory cells is in a not-full state;
associating a first portion of the compound data object with the first group of memory cells;
responsive to determining that the associating the first portion of the compound data object with the first group of memory cells results in the full state of the first group of memory cells, identifying one or more subsequent, in the order corresponding to the sequential logical addresses, groups of memory cells in the not-full state;
associating a second portion of the compound data object with the one or more subsequent groups of memory cells; and
causing the compound data object to be written to the first group of memory cells and the one or more subsequent groups of memory cells, resulting in the full state of the first group of memory cells and at least one of the one or more subsequent groups of memory cells.
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