US 11,809,712 B2
Memory system with threaded transaction support
Frederick A. Ware, Los Altos Hills, CA (US); and Ely Tsern, Los Altos, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Jan. 27, 2022, as Appl. No. 17/586,575.
Application 17/586,575 is a continuation of application No. 16/805,535, filed on Feb. 28, 2020, granted, now 11,249,649.
Application 16/805,535 is a continuation of application No. 15/529,970, granted, now 10,592,120, issued on Mar. 17, 2020, previously published as PCT/US2015/066846, filed on Dec. 18, 2015.
Claims priority of provisional application 62/094,306, filed on Dec. 19, 2014.
Prior Publication US 2022/0221989 A1, Jul. 14, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G11C 5/04 (2006.01); G11C 7/10 (2006.01); G06F 12/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0634 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/0607 (2013.01); G11C 5/04 (2013.01); G11C 7/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A buffer circuit, comprising:
a primary interface for coupling to a group of links associated with a memory controller, the primary signaling interface operating at a primary data signaling rate;
a secondary interface including a first signal path for coupling to a first memory device, and a second signal path for coupling to a second memory device, the first and second signal paths operating at a secondary data signaling rate;
wherein during a first mode of operation, the primary data signaling rate is at least twice the secondary data signaling rate, and wherein a first time interval associated with a transfer of first information via the first signal path temporally overlaps a second time interval involving second information transferred via the second signal path.