US 11,809,710 B2
Outstanding transaction monitoring for memory sub-systems
Dhawal Bavishi, San Jose, CA (US); Robert M. Walker, Raleigh, NC (US); and Laurent Isenegger, Morgan Hill, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,060.
Prior Publication US 2023/0098454 A1, Mar. 30, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first controller configured to:
adjust a count of a number of first transactions and adjust a count of a number of second transactions, wherein the count of the number of first transactions and the count of the number of second transactions are adjusted when:
a first transaction or a second transaction is received by a second controller; or
the first transaction or the second transaction is executed by the second controller; and
send a signal to a traffic generator to limit a number of first transactions sent by the traffic generator to the first controller and limit a number of second transactions sent by the traffic generator to the first controller in response to the first controller detecting a first transaction queue and a second transaction queue are reaching a particular quantity of total transactions; and
wherein the second controller is coupled to the first controller and configured to:
limit the number of first transactions to a particular quantity of outstanding first transactions;
limit the number of second transactions to a particular quantity of outstanding second transactions; and
limit a number of total transactions to a particular quantity of outstanding total transactions.