US 11,809,706 B2
Memory management method, memory storage device, and memory control circuit unit
Yu-Siang Yang, New Taipei (TW); Yu-Cheng Hsu, Yilan County (TW); Tsai-Hao Kuo, Tainan (TW); Wei Lin, Taipei (TW); and An-Cheng Liu, Taipei (TW)
Assigned to PHISON ELECTRONICS CORP., Miaoli (TW)
Filed by PHISON ELECTRONICS CORP., Miaoli (TW)
Filed on Jun. 17, 2021, as Appl. No. 17/349,918.
Claims priority of application No. 110114836 (TW), filed on Apr. 26, 2021.
Prior Publication US 2022/0342547 A1, Oct. 27, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory management method, applicable to a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module, and the rewritable non-volatile memory module comprises a plurality of physical units, the memory management method comprising:
reading first data from a first physical unit among the physical units by using a first read voltage level according to first management information among a plurality of candidate management information;
decoding the first data and recording first error bit information of the first data, wherein the first error bit information reflects a total number of error bits in the first data; and
in response to that the total number of the error bits in the first data is greater than a first threshold and the first data is successfully decoded, adjusting sorting information related to the candidate management information according to the first error bit information which reflects the total number of the error bits in the first data, wherein the sorting information reflects a usage order of the candidate management information in a decoding operation.