US 11,809,552 B2
Systems, methods, and apparatuses for intrusion detection and analytics using power characteristics such as side-channel information collection
Carlos R. Aguayo Gonzalez, Reston, VA (US); Jeffrey H. Reed, Blacksburg, VA (US); and Steven C. Chen, Potomac, MD (US)
Assigned to Power Fingerprinting Inc., Vienna, VA (US)
Filed by Power Fingerprinting Inc., Vienna, VA (US)
Filed on Apr. 5, 2021, as Appl. No. 17/222,596.
Application 17/222,596 is a division of application No. 16/219,438, filed on Dec. 13, 2018, granted, now 10,970,387.
Application 14/881,862 is a division of application No. 14/720,497, filed on May 22, 2015, granted, now 9,268,938, issued on Feb. 23, 2016.
Application 16/219,438 is a continuation of application No. 15/167,772, filed on May 27, 2016, granted, now 10,157,278, issued on Dec. 18, 2018.
Application 15/167,772 is a continuation of application No. 14/881,862, filed on Oct. 13, 2015, granted, now 9,411,009, issued on Aug. 9, 2016.
Prior Publication US 2022/0075869 A1, Mar. 10, 2022
Int. Cl. G06F 21/55 (2013.01); G01R 22/00 (2006.01); G06F 21/32 (2013.01); G06F 21/75 (2013.01); G01R 1/04 (2006.01); G01R 31/28 (2006.01); G01R 21/00 (2006.01)
CPC G06F 21/552 (2013.01) [G01R 21/00 (2013.01); G01R 31/2832 (2013.01); G01R 31/2887 (2013.01); G01R 31/2891 (2013.01); G01R 31/2893 (2013.01); G06F 21/32 (2013.01); G06F 21/755 (2017.08); G01R 1/0408 (2013.01); G01R 31/2886 (2013.01); G06F 2221/034 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a circuit anomaly detector configured to monitor a side-channel output from a target circuit chip over a plurality of times to define a time-related performance of the target device, the circuit anomaly detector configured to detect an anomaly at the target device to define a detected anomaly based on at least one of (1) the time-related performance of the target device, or (2) the time-related performance of the target device and a time-related performance of a plurality of devices similar to or common as the target device; and
a notification processor communicatively coupled to the circuit anomaly detector, the notification processor configured to send a notification message to a device designated to respond to the detected anomaly,
the plurality of times includes a time of an initial manufacture of the target circuit chip, a time the target circuit chip is installed on a printed circuit board assembly (PCBA), and a time the PCBA is installed in a device.