US 11,809,549 B2
Apparatus and method for power virus protection in a processor
Alexander Gendler, Kiriat Motzkin (IL); Sagi Meller, Zichron Yaakov (IL); Gavri Berger, Haifa (IL); and Igor Yanover, Yokneam Illit (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 27, 2019, as Appl. No. 16/728,843.
Prior Publication US 2021/0200860 A1, Jul. 1, 2021
Int. Cl. G06F 21/00 (2013.01); G06F 21/54 (2013.01); G06F 1/32 (2019.01); G06F 21/56 (2013.01); G06F 9/38 (2018.01)
CPC G06F 21/54 (2013.01) [G06F 1/32 (2013.01); G06F 9/3802 (2013.01); G06F 21/561 (2013.01); G06F 2221/034 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor comprising:
first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction;
detection circuitry to detect one or more instructions of a particular type and/or width;
evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry on performance of the processor to determine whether to enable the PVP circuitry, wherein upon being enabled, the PVP circuitry is to determine whether to trigger one or more throttling operations when executing the one or more instructions based on the detected instruction types and/or widths; and
control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.