US 11,809,369 B2
Event messaging in a system having a self-scheduling processor and a hybrid threading fabric
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 3, 2021, as Appl. No. 17/392,550.
Application 17/392,550 is a continuation of application No. 16/399,672, filed on Apr. 30, 2019, granted, now 11,126,587.
Claims priority of provisional application 62/667,699, filed on May 7, 2018.
Prior Publication US 2021/0365403 A1, Nov. 25, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/82 (2006.01); G06F 9/30 (2018.01); G06F 13/40 (2006.01); G06F 12/0875 (2016.01); G06F 9/54 (2006.01); G06F 9/48 (2006.01)
CPC G06F 15/82 (2013.01) [G06F 9/30101 (2013.01); G06F 9/485 (2013.01); G06F 9/4881 (2013.01); G06F 9/542 (2013.01); G06F 9/546 (2013.01); G06F 12/0875 (2013.01); G06F 13/4027 (2013.01); G06F 2212/452 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a processor core configured to execute a plurality of instructions;
an interconnection network interface coupleable to an interconnection network, the interconnection network interface configured to receive a work descriptor data packet, to receive an event data packet, and to decode the received event data packet into an event number;
a thread control memory comprising a thread identifier pool register configured to store a plurality of thread identifiers, a program count register configured to store an initial program count, and a data cache or a general-purpose register configured to store a received first argument;
an execution queue coupled to the thread control memory, the execution queue configured to store one or more thread identifiers, of the plurality of thread identifiers; and
a control logic and thread selection circuit coupled to the execution queue, the control logic and thread selection circuit configured, in response to receiving the work descriptor data packet having the initial program count and the received first argument, to assign a thread identifier of the plurality of thread identifiers to a corresponding execution thread of a plurality of execution threads, to place the thread identifier in the execution queue, and to periodically select the thread identifier of the one or more thread identifiers in the execution queue for execution by the processor core of an instruction of the corresponding execution thread, of the plurality of instructions, the processor core configured to automatically commence execution of the single instruction corresponding to the initial program count and using the received first argument;
wherein the processor core is further configured to execute a first event listen instruction having a waiting mode, of the plurality of instructions, to pause execution of a first selected execution thread of the plurality of execution threads until a corresponding event is received, and is further configured to execute a second event listen instruction having a non-waiting mode, of the plurality of instructions, for a second selected execution thread of the plurality of execution threads to poll a memory location for the corresponding event.