US 11,809,343 B2
Transporting request types with different latencies
Tony M. Brewer, Plano, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 6, 2022, as Appl. No. 17/961,229.
Application 17/961,229 is a continuation of application No. 17/459,525, filed on Aug. 27, 2021, granted, now 11,481,343.
Claims priority of provisional application 63/170,210, filed on Apr. 2, 2021.
Prior Publication US 2023/0033452 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/4027 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory-compute node comprising:
a hybrid threading processor;
a memory controller;
a fabric interface; and
a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller,
wherein the fabric interface supports a first virtual channel (VC0) and a second virtual channel (VC1) to the NOC, and supports the first virtual channel (VC0), the second virtual channel (VC1), and a third virtual channel (VC2) to a scale fabric, and
wherein the fabric interface configured to:
receive, from the hybrid threading processor, a first message that includes a memory request to a destination memory controller, on the second virtual channel over the NOC; and
transmit the first message to the destination memory controller across the scale fabric via the first virtual channel or the third virtual channel depending on a latency characteristic of the first message.