CPC G06F 13/1668 (2013.01) [G06F 13/4027 (2013.01)] | 25 Claims |
1. A memory-compute node comprising:
a hybrid threading processor;
a memory controller;
a fabric interface; and
a network on chip (NOC) that provides communication between the hybrid threading processor, the fabric interface, and the memory controller,
wherein the fabric interface supports a first virtual channel (VC0) and a second virtual channel (VC1) to the NOC, and supports the first virtual channel (VC0), the second virtual channel (VC1), and a third virtual channel (VC2) to a scale fabric, and
wherein the fabric interface configured to:
receive, from the hybrid threading processor, a first message that includes a memory request to a destination memory controller, on the second virtual channel over the NOC; and
transmit the first message to the destination memory controller across the scale fabric via the first virtual channel or the third virtual channel depending on a latency characteristic of the first message.
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