US 11,809,337 B2
Graphics processing device
Yi-Cheng Chen, Hsinchu (TW); and Hsu-Jung Tung, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on May 27, 2021, as Appl. No. 17/331,673.
Claims priority of application No. 109124794 (TW), filed on Jul. 22, 2020.
Prior Publication US 2022/0027293 A1, Jan. 27, 2022
Int. Cl. G06F 13/16 (2006.01); G06T 1/20 (2006.01)
CPC G06F 13/1652 (2013.01) [G06T 1/20 (2013.01); G06F 2213/0038 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A graphics processing device comprising circuit chips and an external circuit, each of the circuit chips being a system on a chip (SoC), and the circuit chips being configured to cooperate and including a first SoC and a second SoC, wherein:
the first SoC includes:
a first graphics processing unit (GPU) configured to divide to-be-processed data into multiple input parts including a first input part and a second input part in a performance-enhancing mode, and to process the first input part to generate and output first output data in the performance-enhancing mode; and
a first transceiver circuit coupled to the first GPU, and configured to transmit the second input part to the second SoC via the external circuit in the performance-enhancing mode, and further configured to receive second output data from the external circuit to forward the second output data in the performance-enhancing mode;
the external circuit is set outside any of the first SoC and the second SoC; and
the second SoC includes:
a second transceiver circuit configured to receive the second input part from the external circuit in the performance-enhancing mode, and further configured to transmit the second output data to the first SoC via the external circuit in the performance-enhancing mode; and
a second GPU coupled to the second transceiver circuit, and configured to receive and process the second input part to generate the second output data in the performance-enhancing mode, and then output the second output data to the second transceiver circuit in the performance-enhancing mode.