US 11,809,322 B2
Region based directory scheme to adapt to large cache sizes
Vydhyanathan Kalyanasundharam, Santa Clara, CA (US); Kevin M. Lepak, Austin, TX (US); Amit P. Apte, Austin, TX (US); Ganesh Balakrishnan, Austin, TX (US); Eric Christopher Morton, Austin, TX (US); Elizabeth M. Cooper, Los Gatos, CA (US); and Ravindra N. Bhargava, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 13, 2021, as Appl. No. 17/472,977.
Application 17/472,977 is a continuation of application No. 15/846,008, filed on Dec. 18, 2017, granted, now 11,119,926, issued on Sep. 14, 2021.
Prior Publication US 2021/0406180 A1, Dec. 30, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0817 (2016.01); G06F 12/128 (2016.01); G06F 12/0811 (2016.01); G06F 12/0871 (2016.01); G06F 12/0831 (2016.01)
CPC G06F 12/0817 (2013.01) [G06F 12/0811 (2013.01); G06F 12/0831 (2013.01); G06F 12/0871 (2013.01); G06F 12/128 (2013.01); G06F 2212/283 (2013.01); G06F 2212/604 (2013.01); G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a cache directory configured to:
maintain, in first storage, an entry for each region of memory which has at least one cache line cached in any of a plurality of cache subsystems, wherein a region comprises a plurality of cache lines;
maintain a count that indicates how many cache lines of a given region are cached; and
allocate an entry in a second storage to track the given region on a finer granularity basis, responsive to detecting the count has exceeded a threshold, wherein the finer granularity basis is a sub-region basis.