US 11,809,317 B2
Memory controlling device and memory system including the same
Myoungsoo Jung, Daejeon (KR); Gyuyoung Park, Daejeon (KR); and Miryeong Kwon, Incheon (KR)
Assigned to MemRay Corporation, Seoul (KR); and Yonsei University, University—Industry Foundation (UIF), Seoul (KR)
Filed by MemRay Corporation, Seongnam-si (KR); and Yonsei University, University-Industry Foundation (UIF), Seoul (KR)
Filed on Feb. 24, 2022, as Appl. No. 17/679,654.
Application 17/679,654 is a continuation of application No. 16/860,801, filed on Apr. 28, 2020, granted, now 11,288,192.
Application 16/860,801 is a continuation of application No. 16/250,343, filed on Jan. 17, 2019, granted, now 10,664,394.
Claims priority of application No. 10-2018-0042372 (KR), filed on Apr. 11, 2018; and application No. 10-2018-0067739 (KR), filed on Jun. 12, 2018.
Prior Publication US 2022/0214969 A1, Jul. 7, 2022
Int. Cl. G06F 12/08 (2016.01); G11C 14/00 (2006.01); G11C 13/00 (2006.01); G06F 12/0804 (2016.01); G06F 12/0895 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/0804 (2013.01) [G06F 12/0895 (2013.01); G11C 14/0045 (2013.01); G06F 13/1694 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01); G11C 13/0069 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method for a memory controller, for controlling a first memory module, including a memory cell array partitioned into a plurality of partitions, and a second memory module, used as a cache including a plurality of cache lines, comprising:
determining, for an incoming first read request for first target data, with lookup logic, whether the first read request is a cache hit or miss;
determining the first read request is a cache miss;
determining, for the memory cell array being resistance switching, the first read request targets a first partition for the first target data;
reading the first target data, when a write is in progress, if the write is to a second partition different from the first partition; and
suspending the reading of the first target data, when the read request is the cache miss and when the write in progress is to the first partition.