CPC G06F 12/0804 (2013.01) [G06F 12/0895 (2013.01); G11C 14/0045 (2013.01); G06F 13/1694 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/608 (2013.01); G11C 13/0069 (2013.01)] | 12 Claims |
1. A method for a memory controller, for controlling a first memory module, including a memory cell array partitioned into a plurality of partitions, and a second memory module, used as a cache including a plurality of cache lines, comprising:
determining, for an incoming first read request for first target data, with lookup logic, whether the first read request is a cache hit or miss;
determining the first read request is a cache miss;
determining, for the memory cell array being resistance switching, the first read request targets a first partition for the first target data;
reading the first target data, when a write is in progress, if the write is to a second partition different from the first partition; and
suspending the reading of the first target data, when the read request is the cache miss and when the write in progress is to the first partition.
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