US 11,808,810 B2
AT-speed test access port operations
Lee D. Whetsel, Parker, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Feb. 20, 2023, as Appl. No. 18/111,679.
Application 18/111,679 is a division of application No. 17/692,057, filed on Mar. 10, 2022, granted, now 11,585,852.
Application 17/692,057 is a division of application No. 17/117,532, filed on Dec. 10, 2020, granted, now 11,287,473, issued on Mar. 29, 2022.
Application 17/117,532 is a division of application No. 16/689,764, filed on Nov. 20, 2019, granted, now 10,895,598, issued on Jan. 19, 2021.
Application 16/689,764 is a division of application No. 16/183,347, filed on Nov. 7, 2018, granted, now 10,520,551, issued on Dec. 21, 2019.
Application 16/183,347 is a division of application No. 15/626,446, filed on Jun. 19, 2017, granted, now 10,156,608, issued on Dec. 18, 2018.
Application 15/626,446 is a division of application No. 15/336,101, filed on Oct. 27, 2016, granted, now 9,733,308, issued on Aug. 15, 2017.
Application 15/336,101 is a division of application No. 14/830,244, filed on Aug. 19, 2015, granted, now 9,507,679, issued on Nov. 29, 2016.
Application 14/830,244 is a division of application No. 14/179,754, filed on Feb. 13, 2014, granted, now 9,146,825, issued on Sep. 19, 2015.
Application 14/179,754 is a division of application No. 13/188,078, filed on Jul. 21, 2011, granted, now 8,694,844, issued on Apr. 8, 2014.
Claims priority of provisional application 61/406,674, filed on Oct. 26, 2010.
Claims priority of provisional application 61/368,906, filed on Jul. 29, 2010.
Prior Publication US 2023/0194604 A1, Jun. 22, 2023
Int. Cl. G01R 31/3185 (2006.01); G06F 11/26 (2006.01); G01R 31/3177 (2006.01); H10K 50/814 (2023.01); H10K 50/816 (2023.01); H10K 50/844 (2023.01); H10K 59/122 (2023.01); H10K 59/123 (2023.01); H10K 59/124 (2023.01); H10K 59/121 (2023.01); H10K 71/00 (2023.01); G01R 31/317 (2006.01); H10K 59/12 (2023.01); H10K 102/00 (2023.01); H10K 102/10 (2023.01); H01L 27/12 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31727 (2013.01); G01R 31/318555 (2013.01); G01R 31/318572 (2013.01); G06F 11/26 (2013.01); H10K 50/814 (2023.02); H10K 50/816 (2023.02); H10K 50/844 (2023.02); H10K 59/122 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 59/1213 (2023.02); H10K 71/00 (2023.02); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H10K 59/1201 (2023.02); H10K 2102/00 (2023.02); H10K 2102/103 (2023.02)] 13 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a TDI input, a TDO output, a TCK input and a TMS input;
a TAP state machine (TSM) including an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and TSM state detecting circuitry;
an instruction register including an input coupled to the TDI input, a first output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine;
a multiplexer including a first input coupled to the TSM state detecting circuitry, and a multiplexer output;
router circuitry including a TSM DRC input coupled to the TSM DRC output, a multiplexer DRC input coupled to the multiplexer output, and a router DRC output; and
a data register including an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.