CPC G01R 31/3177 (2013.01) [G01R 31/31723 (2013.01); G01R 31/31727 (2013.01); G01R 31/318555 (2013.01); G01R 31/318572 (2013.01); G06F 11/26 (2013.01); H10K 50/814 (2023.02); H10K 50/816 (2023.02); H10K 50/844 (2023.02); H10K 59/122 (2023.02); H10K 59/123 (2023.02); H10K 59/124 (2023.02); H10K 59/1213 (2023.02); H10K 71/00 (2023.02); H01L 27/1222 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H10K 59/1201 (2023.02); H10K 2102/00 (2023.02); H10K 2102/103 (2023.02)] | 13 Claims |
1. An integrated circuit comprising:
a TDI input, a TDO output, a TCK input and a TMS input;
a TAP state machine (TSM) including an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and TSM state detecting circuitry;
an instruction register including an input coupled to the TDI input, a first output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine;
a multiplexer including a first input coupled to the TSM state detecting circuitry, and a multiplexer output;
router circuitry including a TSM DRC input coupled to the TSM DRC output, a multiplexer DRC input coupled to the multiplexer output, and a router DRC output; and
a data register including an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.
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