US 11,808,798 B2
Jitter noise detector
Tien-Chien Huang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Oct. 24, 2022, as Appl. No. 17/972,475.
Application 17/972,475 is a division of application No. 16/952,744, filed on Nov. 19, 2020, granted, now 11,513,147.
Application 16/952,744 is a continuation of application No. 15/944,217, filed on Apr. 3, 2018, granted, now 10,845,404.
Claims priority of provisional application 62/525,656, filed on Jun. 27, 2017.
Prior Publication US 2023/0040034 A1, Feb. 9, 2023
Int. Cl. G01R 29/26 (2006.01); H03L 7/08 (2006.01); H03L 7/07 (2006.01); H03K 19/0185 (2006.01); G01R 31/317 (2006.01); G01R 29/027 (2006.01)
CPC G01R 29/26 (2013.01) [G01R 31/31709 (2013.01); H03K 19/01855 (2013.01); H03L 7/07 (2013.01); H03L 7/08 (2013.01); G01R 29/0276 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A noise detection circuit, comprising:
a first component configured to receive a clock signal;
a second component configured to receive a reference clock signal, wherein the first and second components each comprises an n-type metal-oxide-semiconductor (NMOS) field-effect-transistor (FET);
a latch circuit, coupled to the first component at a first node and coupled to the second component at a second node, and configured to latch logic states of voltage levels at the first and second nodes, respectively, based on a timing difference between transition edges of the clock signal and the reference clock signal; and
a plurality of capacitors coupled between the first and second nodes.