| CPC A61B 1/00009 (2013.01) [A61B 1/00006 (2013.01); A61B 1/00045 (2013.01); A61B 1/043 (2013.01); A61B 1/045 (2013.01); A61B 1/05 (2013.01); A61B 1/0661 (2013.01)] | 13 Claims |
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1. A control apparatus comprising:
a processor configured to:
generate a clock at predetermined timing;
generate a plurality of first white light images of an object based on obtained first signals at timing at which the object is irradiated with white light, based on the generated clock, the generating of the plurality of first white light images comprising generating a first white light image at a first clock, generating a second white light image at a third clock, and generating a third white light image at a fourth clock;
generate a plurality of fluorescent images of the object based on obtained second signals at timing at which the object is irradiated with excitation light, based on the generated clock, the generating of the plurality of fluorescent images comprising generating a first fluorescent image at a second clock,
superimpose each of at least the second white light image and the third white light image of the generated plurality of first white light images and the generated first fluorescent image to generate a plurality of first superimposed images, based on the generated clock, the plurality of first superimposed images comprising a first superimposed image superimposing the second white light image and the first fluorescent image at the fourth clock and a second superimposed image superimposing the third white light image and the first fluorescent image at a fifth clock; and
subsequent to generating at least the first superimposed image and the second superimposed image, generate a second fluorescent image;
wherein the first clock, the second clock, the third clock, the fourth clock and the fifth clock are sequential.
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