US 10,462,911 B2
High-current transmitting method utilizing printed circuit board
Chang Hui Lee, Cheonan-Si (KR); and Dong Hyun Kim, Sejong-Si (KR)
Assigned to LG CHEM, LTD., Seoul (KR)
Appl. No. 15/758,217
Filed by LG CHEM, LTD., Seoul (KR)
PCT Filed Mar. 21, 2017, PCT No. PCT/KR2017/003005
§ 371(c)(1), (2) Date Mar. 7, 2018,
PCT Pub. No. WO2017/213333, PCT Pub. Date Dec. 14, 2017.
Claims priority of application No. 10-2016-0070347 (KR), filed on Jun. 7, 2016.
Prior Publication US 2018/0255648 A1, Sep. 6, 2018
Int. Cl. H05K 1/11 (2006.01); H05K 3/42 (2006.01); H05K 3/06 (2006.01); H05K 1/09 (2006.01); H05K 3/00 (2006.01); H05K 3/28 (2006.01); H05K 3/46 (2006.01); H05K 1/02 (2006.01); H05K 3/34 (2006.01)
CPC H05K 3/42 (2013.01) [H05K 1/0265 (2013.01); H05K 1/09 (2013.01); H05K 1/115 (2013.01); H05K 3/0011 (2013.01); H05K 3/06 (2013.01); H05K 3/282 (2013.01); H05K 3/429 (2013.01); H05K 3/462 (2013.01); H05K 3/4623 (2013.01); H05K 3/4644 (2013.01); H05K 3/3447 (2013.01); H05K 2201/09572 (2013.01); H05K 2203/0502 (2013.01); H05K 2203/0548 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A multilayer printed circuit board each layer of which is printed with a circuit pattern, the multilayer printed circuit board comprising via holes for connecting circuits of each layer, wherein each via hole is a through hole having a pair of open ends, and wherein each via hole comprises:
a plating layer formed on a side wall of the via hole, the plating layer including a Cu plating layer plated with Cu on the side wall of the via hole and an Au plating layer formed on the Cu plating layer; and
a solder cream on the Au plating layer and filled in a vacant surface of the via holes on which the plating layer is formed.