US 10,462,894 B2
Circuit board
Joel R. Goergen, Maple Grove, MN (US); and Yi Zheng, Cold Spring, MN (US)
Assigned to Force10 Networks, Inc., San Jose, CA (US)
Filed by FORCE10 NETWORKS, INC., San Jose, CA (US)
Filed on Nov. 26, 2014, as Appl. No. 14/555,227.
Application 12/961,610 is a division of application No. 12/151,088, filed on May 2, 2008, granted, now 8,168,891, issued on May 1, 2012.
Application 14/555,227 is a continuation of application No. 12/961,610, filed on Dec. 7, 2010, granted, now 8,898,891.
Application 12/151,088 is a continuation in part of application No. 11/977,783, filed on Oct. 26, 2007, granted, now 8,304,659, issued on Nov. 6, 2012.
Prior Publication US 2015/0156863 A1, Jun. 4, 2015
This patent is subject to a terminal disclaimer.
Int. Cl. H05K 1/00 (2006.01); H05K 1/02 (2006.01); H01P 3/08 (2006.01); H05K 3/00 (2006.01); H05K 3/46 (2006.01); H05K 1/03 (2006.01)
CPC H05K 1/0216 (2013.01) [H01P 3/081 (2013.01); H05K 1/024 (2013.01); H05K 1/0242 (2013.01); H05K 1/0245 (2013.01); H05K 1/0298 (2013.01); H05K 3/0091 (2013.01); H05K 3/46 (2013.01); B32B 2305/076 (2013.01); B32B 2309/08 (2013.01); B32B 2457/08 (2013.01); H05K 1/0366 (2013.01); H05K 3/4611 (2013.01); H05K 2201/0187 (2013.01); H05K 2201/029 (2013.01); H05K 2201/098 (2013.01); H05K 2201/09236 (2013.01); H05K 2201/09745 (2013.01); Y10T 29/49117 (2015.01); Y10T 29/49126 (2015.01); Y10T 29/49128 (2015.01); Y10T 29/49156 (2015.01); Y10T 29/49165 (2015.01)] 22 Claims
OG exemplary drawing
 
1. A circuit board, comprising:
a first board dielectric layer;
a second board dielectric layer that is located adjacent the first board dielectric layer;
a first local dielectric region that is located within the first board dielectric layer and adjacent the second board dielectric layer;
a second local dielectric region that is located within the second board dielectric layer and adjacent at least the first local dielectric region within the first board dielectric layer; and
a pair of differential conductors that are each located within at least one of the first board dielectric layer and the second board dielectric layer, within at least one of the first local dielectric region and the second local dielectric region, such that the pair of differential conductors are positioned immediately adjacent both the first local dielectric region and the second local dielectric region,
wherein the first local dielectric region and the second local dielectric region are configured with dielectric constants that are different than dielectric constants of the first board dielectric layer and the second board dielectric layer such that crosstalk between the pair of differential conductors and a third conductor located within at least one of the first board dielectric layer and the second board dielectric layer is reduced.