US 11,793,091 B2
Semiconductor structure and manufacturing method thereof
Shih-Wei Su, Tainan (TW); Da-Jun Lin, Kaohsiung (TW); Chih-Wei Chang, Tainan (TW); Bin-Siang Tsai, Changhua County (TW); and Ting-An Chien, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Dec. 7, 2020, as Appl. No. 17/114,438.
Claims priority of application No. 202011221313.1 (CN), filed on Nov. 5, 2020.
Prior Publication US 2022/0140239 A1, May 5, 2022
Int. Cl. H01L 45/00 (2006.01); H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/063 (2023.02) [H10B 63/00 (2023.02); H10N 70/028 (2023.02); H10N 70/041 (2023.02); H10N 70/841 (2023.02); H10N 70/8833 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a substrate;
forming a resistance random access memory on the substrate, wherein the resistance random access memory comprises an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode; and
forming a cap layer on the resistance random access memory, wherein the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.