US 11,793,031 B2
Display device
Young In Hwang, Yongin-si (KR); Ji Hye Kong, Yongin-si (KR); Suk Hoon Ku, Yongin-si (KR); Sung Wook Kim, Yongin-si (KR); Jin A Lee, Yongin-si (KR); and Yun Sik Joo, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Jun. 2, 2022, as Appl. No. 17/831,297.
Application 17/831,297 is a division of application No. 16/823,119, filed on Mar. 18, 2020, granted, now 11,362,161.
Claims priority of application No. 10-2019-0069610 (KR), filed on Jun. 12, 2019.
Prior Publication US 2022/0302237 A1, Sep. 22, 2022
Int. Cl. H01L 23/00 (2006.01); H10K 59/121 (2023.01); G09G 3/3233 (2016.01); H01L 29/786 (2006.01); G09G 3/20 (2006.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); H01L 27/12 (2006.01)
CPC H10K 59/1213 (2023.02) [G09G 3/3233 (2013.01); G09G 3/2007 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0809 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0247 (2013.01); H01L 27/1251 (2013.01); H01L 29/78696 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A display device comprising:
pixels,
wherein each of the pixels comprises:
a first transistor comprising a first gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node;
a second transistor comprising a second gate electrode connected to a first scan line, a third electrode connected to a data line, and a fourth electrode connected to the second node;
a third transistor comprising a third gate electrode connected to the first scan line, a fifth electrode connected to the first node, and a sixth electrode connected to the third node;
a first sub-transistor comprising a fourth gate electrode connected to a second scan line, a seventh electrode connected to the first node, and a eighth electrode connected to a fifth node; and
a second sub-transistor comprising a fifth gate electrode connected to the second scan line, a ninth electrode connected to the fifth node, and a tenth electrode connected to an initialization line, and
wherein a channel width of the first sub-transistor is wider than a channel width of the second sub-transistor.