CPC H10B 63/84 (2023.02) [H01L 21/268 (2013.01); H01L 21/6835 (2013.01); H01L 21/76254 (2013.01); H01L 21/8221 (2013.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 27/0688 (2013.01); H01L 27/1203 (2013.01); H01L 27/1211 (2013.01); H01L 29/42392 (2013.01); H01L 29/785 (2013.01); H01L 29/7841 (2013.01); H10B 10/00 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 41/20 (2023.02); H10B 41/41 (2023.02); H10B 43/20 (2023.02); H10B 61/22 (2023.02); H10B 63/30 (2023.02); H10B 63/845 (2023.02); H01L 27/105 (2013.01); H01L 2029/7857 (2013.01); H01L 2221/6835 (2013.01); H10B 12/056 (2023.02); H10B 12/36 (2023.02); H10B 41/40 (2023.02); H10B 43/40 (2023.02); H10N 70/20 (2023.02); H10N 70/823 (2023.02); H10N 70/8833 (2023.02)] | 20 Claims |
1. A semiconductor device, the device comprising:
a plurality of transistors,
wherein at least one of said plurality of transistors comprises a first single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a second single crystal source, channel, and drain,
wherein said second single crystal source, channel, and drain is disposed above said first single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a third single crystal source, channel, and drain,
wherein said third single crystal source, channel, and drain is disposed above said second single crystal source, channel, and drain,
wherein at least one of said plurality of transistors comprises a fourth single crystal source, channel, and drain, and
wherein said fourth single crystal source, channel, and drain is disposed above said third single crystal source, channel, and drain; and
a first gate structure,
wherein said first gate structure controls at least one of said first single crystal channels and at least one of said second single crystal channels.
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