US 11,792,997 B1
Common mode compensation for differential multi-element non-linear polar material based gain memory bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 3, 2021, as Appl. No. 17/517,945.
Application 17/517,945 is a continuation of application No. 17/516,293, filed on Nov. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 53/30 (2023.01); G11C 11/22 (2006.01); H01L 25/065 (2023.01); H10B 53/40 (2023.01)
CPC H10B 53/30 (2023.02) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H01L 25/0655 (2013.01); H10B 53/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first bit-cell comprising:
a first transistor coupled to a first bit-line and controllable by a word-line; and
a second transistor coupled to a first select-line and the first transistor, wherein the first transistor and the second transistor are coupled to:
a first capacitor comprising a non-linear polar material,
a second capacitor comprising the non-linear polar material, and
a third capacitor comprising linear a linear dielectric material, wherein the first capacitor is coupled to a first plate-line, wherein the second capacitor is coupled to a second plate-line, wherein the third capacitor is coupled to a third plate-line, and wherein the apparatus further comprises:
a second bit-cell comprising:
a third transistor coupled to a second bit-line and controllable by the word-line;
a fourth transistor coupled to a second select-line and the third transistor, wherein the third transistor and the fourth transistor are coupled to:
a fourth capacitor comprising the non-linear polar material,
a fifth capacitor comprising the non-linear polar material, and
a sixth capacitor comprising the linear dielectric material, wherein the fourth capacitor is coupled to a fourth plate-line, wherein the fifth capacitor is coupled to a fifth plate-line, and wherein the sixth capacitor is coupled to a sixth plate-line.