CPC H10B 53/30 (2023.02) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H01L 25/0655 (2013.01); H10B 53/40 (2023.02)] | 20 Claims |
1. An apparatus comprising:
a first bit-cell comprising:
a first transistor coupled to a first bit-line and controllable by a word-line; and
a second transistor coupled to a first select-line and the first transistor, wherein the first transistor and the second transistor are coupled to:
a first capacitor comprising a non-linear polar material,
a second capacitor comprising the non-linear polar material, and
a third capacitor comprising linear a linear dielectric material, wherein the first capacitor is coupled to a first plate-line, wherein the second capacitor is coupled to a second plate-line, wherein the third capacitor is coupled to a third plate-line, and wherein the apparatus further comprises:
a second bit-cell comprising:
a third transistor coupled to a second bit-line and controllable by the word-line;
a fourth transistor coupled to a second select-line and the third transistor, wherein the third transistor and the fourth transistor are coupled to:
a fourth capacitor comprising the non-linear polar material,
a fifth capacitor comprising the non-linear polar material, and
a sixth capacitor comprising the linear dielectric material, wherein the fourth capacitor is coupled to a fourth plate-line, wherein the fifth capacitor is coupled to a fifth plate-line, and wherein the sixth capacitor is coupled to a sixth plate-line.
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