US 11,792,990 B2
Methods of manufacturing vertical memory devices
Yujin Seo, Suwon-si (KR); Byoungil Lee, Suwon-si (KR); Subin Kang, Suwon-si (KR); and Jimo Gu, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 29, 2021, as Appl. No. 17/514,331.
Application 17/514,331 is a division of application No. 16/749,110, filed on Jan. 22, 2020, granted, now 11,164,887.
Claims priority of application No. 10-2019-0054233 (KR), filed on May 9, 2019.
Prior Publication US 2022/0052074 A1, Feb. 17, 2022
Int. Cl. H01L 27/11582 (2017.01); H10B 43/27 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method of manufacturing a vertical memory device, the method comprising:
sequentially forming a sacrificial layer structure and a support layer on a substrate;
alternately and repeatedly stacking an insulation layer and a sacrificial layer on the support layer;
forming a channel through the sacrificial layer structure, the support layer, the insulation layer, and the sacrificial layer to contact an upper surface of the substrate;
forming a first opening through the insulation layer, the sacrificial layer, and the support layer to expose at least a portion of the sacrificial layer structure;
removing the at least a portion of the sacrificial layer structure exposed by the first opening to form a first gap exposing a portion of a lower surface of the support layer;
oxidizing the exposed portion of the lower surface of the support layer, and removing the oxidized portion;
removing the sacrificial layer structure to form a second gap exposing an outer sidewall of the channel;
forming a channel connecting pattern to partially fill the second gap, the channel connecting pattern surrounding the channel and exposing a portion of the upper surface of the substrate;
oxidizing the exposed portion of the upper surface of the substrate and a sidewall of the channel connecting pattern to form an etch stop pattern;
removing the sacrificial layer to form a third gap; and
forming a gate electrode in the third gap.