CPC H10B 43/27 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 43/35 (2023.02)] | 15 Claims |
1. A semiconductor structure comprising a memory die, wherein the memory die comprises:
an alternating stack of insulating layers and electrically conductive layers overlying a substrate and laterally extending through a series of regions that comprises, in a spatial order along a first horizontal direction, a first memory array region, a first contact region, a central memory array region, a second contact region, and a second memory array region, wherein the electrically conductive layers continuously extend from the first memory array region to the second memory array region;
arrays of memory openings located in the first memory array region, the central memory array region, and the second memory array region; and
arrays of memory opening fill structures located within the arrays of memory openings and comprising a respective vertical stack of memory elements.
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