US 11,792,987 B2
Self-aligned vertical integration of three-terminal memory devices
Thorsten Lill, Santa Clara, CA (US); Meihua Shen, Fremont, CA (US); John Hoang, Fremont, CA (US); Hui-Jung Wu, Pleasanton, CA (US); Gereng Gunawan, Saratoga, CA (US); and Yang Pan, Los Altos, CA (US)
Assigned to LAM RESEARCH CORPORATION, Fremont, CA (US)
Appl. No. 17/283,645
Filed by LAM RESEARCH CORPORATION, Fremont, CA (US)
PCT Filed Oct. 22, 2019, PCT No. PCT/US2019/057418
§ 371(c)(1), (2) Date Apr. 8, 2021,
PCT Pub. No. WO2020/086566, PCT Pub. Date Apr. 30, 2020.
Claims priority of provisional application 62/775,615, filed on Dec. 5, 2018.
Claims priority of provisional application 62/751,089, filed on Oct. 26, 2018.
Prior Publication US 2021/0391355 A1, Dec. 16, 2021
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 51/10 (2023.01); H10B 51/20 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02)] 31 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory structure for memory cells, comprising:
a plurality of oxide layers;
a plurality of word line layers,
wherein the plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction; and
a plurality of double channel holes extending through the plurality of oxide layers and the plurality of word line layers in the first direction,
wherein the plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.