US 11,792,986 B2
Dual sacrificial material replacement process for a three-dimensional memory device and structure formed by the same
Keigo Kitazawa, Nagoya (JP); Naoto Norizuki, Yokkaichi (JP); and Shunsuke Takuma, Yokkaichi (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Apr. 19, 2021, as Appl. No. 17/233,799.
Prior Publication US 2022/0336486 A1, Oct. 20, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/27 (2023.01); H10B 51/20 (2023.01); H10B 63/00 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/27 (2023.02); H10B 51/20 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A memory device, comprising:
an alternating stack of insulating layers and electrically conductive layers;
a memory opening vertically extending through the alternating stack;
a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers;
a backside trench vertically extending through the alternating stack; and
a backside trench fill structure comprising a backside insulating material portion, wherein:
the electrically conductive layers comprise a vertically alternating sequence of first electrically conductive layers and second electrically conductive layers that are interlaced along a vertical direction;
each of the first electrically conductive layers is laterally spaced from the backside insulating material portion by a respective dielectric spacer plate; and
each of the second electrically conductive layers is in direct contact with the backside insulating material portion.