US 11,792,977 B2
Semiconductor memory structure
Hsin-Wen Su, Hsinchu (TW); Shih-Hao Lin, Hsinchu (TW); Yu-Kuan Lin, Taipei (TW); Lien-Jung Hung, Taipei (TW); and Ping-Wei Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 13, 2021, as Appl. No. 17/320,049.
Prior Publication US 2022/0367488 A1, Nov. 17, 2022
Int. Cl. H10B 20/20 (2023.01)
CPC H10B 20/20 (2023.02) 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a program word line and a read word line over an active region, each extending along a line direction, the program word line engaging a first transistor channel and the read word line engaging a second transistor channel;
a first metal line over and electrically connected to the program word line;
a second metal line over and electrically connected to the read word line; and
a bit line over and electrically connected to the active region,
wherein the first metal line and the second metal line are in a metal-0 (M0) interconnect layer,
wherein the program word line has a first width along a channel direction perpendicular to the line direction, the read word line has a second width along the channel direction, and
wherein the first width is less than the second width.