US 11,792,938 B2
Method for fabricating carrier structure
Yu-Lung Huang, Taichung (TW); Chee-Key Chung, Taichung (TW); Chang-Fu Lin, Taichung (TW); and Yuan-Hung Hsu, Taichung (TW)
Assigned to Silicon Precision Industries Co., Ltd., Taichung (TW)
Filed by Siliconware Precision Industries Co., Ltd., Taichung (TW)
Filed on Nov. 2, 2020, as Appl. No. 17/86,888.
Application 17/086,888 is a division of application No. 16/669,872, filed on Oct. 31, 2019, granted, now 10,863,626.
Claims priority of application No. 108131538 (TW), filed on Sep. 2, 2019.
Prior Publication US 2021/0068260 A1, Mar. 4, 2021
Int. Cl. H05K 3/46 (2006.01); H05K 1/18 (2006.01); H05K 1/02 (2006.01); H05K 3/30 (2006.01)
CPC H05K 1/184 (2013.01) [H05K 1/0271 (2013.01); H05K 3/303 (2013.01); H05K 3/4697 (2013.01); H05K 2201/10568 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A method for fabricating a carrier structure, comprising:
providing a substrate, wherein the substrate is defined with a chip mounting region and a surrounding region which surrounds the chip mounting region;
forming a cavity in the substrate;
forming a metal layer on the substrate to cover the cavity acting as a spacer, wherein a hollow portion is formed in the spacer, and the spacer is disposed within the surrounding region and free from communicating with the chip mounting region; and
forming a circuit layer via the metal layer,
wherein the spacer is free from being electrically connected to the circuit layer and surrounds the chip mounting region.